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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:32:26 03/04/2012 
-- Design Name: 
-- Module Name:    DataRegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DataRegister is
    Port ( data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           dr_sel : in  STD_LOGIC;
			  data_sel : in STD_LOGIC; --el enable de data_reg
           dataReg_o : out  STD_LOGIC_VECTOR (7 downto 0));
end DataRegister;

architecture Behavioral of DataRegister is
	signal aux_mux15_16: STD_LOGIC_VECTOR (7 downto 0);
begin
	process (clk)
	begin
		if (rising_edge(clk)) then
			if(data_sel ='1') then --si esta habilitado
				if (dr_sel = '0') then
					aux_mux15_16 <=  data_word_i;
				else
					aux_mux15_16 <= port_word_i;
				end if;
				dataReg_o <= aux_mux15_16;
			end if;
		end if;
	end process;
end Behavioral;